How do you manipulate input arrays in an always block (verilog)? -

i'm new verilog , i'm starting understand how works. want manipulate input module mant[22:0], in block not sure how go it.

module normalize(mant,exp,mant_norm,exp_norm);      input [22:0]mant;     input [7:0]exp;      output [22:0]mant_norm;     output [7:0]exp_norm;      reg mantreg[22:0];     reg count=0;      always@(mant or exp)     begin      mantreg<=mant; //this gives error         if(mant[22]==0)         begin            mant<={mant[21:0],1'b0};//this gives error           count<=count+1;          end      end endmodule 

so have shift mant register if bit22 0 , count number of shifts. confused when use reg , when use wire , how manipulation. please let me know how go it.

as can see in code assigning vector value (mant) array of 23(mantreg). instead should declare mantreg reg [22:0] mantreg (which vector of 23 bit).

wire type variable can not assigned procedurally. used in continues assignment. other way around reg varible can procedural assigned.

for try read out lrm of verilog .