makefile - Linux out of tree module build issue - 


obj-m := $(modname).o ccflags-y := $(ccflags) src_files := $(wildcard $(foreach pat,*.c *.cpp *.s,src/$(pat) src/$(modname)/$(pat))) $(modname)-objs := $(addsuffix .o, $(basename $(src_files)))  all:      make -c $(kdir) m=$(shell pwd) modules  clean:      make -c $(kdir) m=$(shell pwd) clean

i have make file building kernel modules. whenever run it, error saying there no rule make target .c. .c not source file. if remove "if [ -d src ]" check error saying src doesn't exists on recursive make call kernel build system. if specify full path src gives same output saying can't find (which weird). if hard code src_files works (if didn't copy , paste wrong). have idea going on?

in makefile expect current directory 1 contained given makefile. when file executed kbuild context, no longer true: current directory directory kernel sources.

that why content of src_files variable becomes wrong: wildcard cannot find files under src/ in kernel sources. may use special src variable refer directory makefile:

src_files := $(wildcard $(foreach pat,*.c *.cpp *.s,$(src)/src/$(pat) $(src)/src/$(modname)/$(pat)))

from other side, paths enumerated in *-objs variable should relative (this requirement kbuild). need strip prefix these absolute paths:

src_files_rel := $(src_files:$(src)/%=%)

then may use these paths create objects list:

$(modname)-objs := $(addsuffix .o, $(basename $(src_files_rel)))

-

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