verilog code to find a single max value for an input that has 1000 samples values -


i want find single max value input signal has 1000 decimal values read memory once every positive clk edge.i did following rough code finding max value didn't give me correct max value/number please me can find single max value in these 1000 values of input signal..`thanks in advance

module(input clk, input [15:0]din, output [15:0]dout); reg [15:0] max=0;  @ (posedge clk) if(din>max) max<=din; else max<=0;  assign dout=max; endmodule 

assumption 1:

if memory read operation of 1000 valuation out of finding max value module no need track how many values read.

module find_max (input         clk,                   input  [15:0] din,                   output [15:0] dout                );  reg [15:0] max=0;  @ (posedge clk) begin   if(din > max)     max <= din;   else     max <= max; end  assign dout = max;  endmodule 

your max value reflected in output after next cycle of being fed find_max module.

assumption 2:

if outof find_max module not taking care of total number of valuation read required 1 counter track number of cycles or valuation arrived.

module find_max (input         clk,                   input  [15:0] din,                   output [15:0] dout                );  reg [15:0] max=0; reg [ 9:0] cnt=0;  @ (posedge clk) begin   cnt <= cnt + 1'b1;   if(din > max)     max <= din;   else     max <= max; end  assign dout = (cnt == 10'd1000) ? max : 16'd0;  endmodule 

we need not store value of 1000 sample because have find max value.


Comments

Popular posts from this blog

PySide and Qt Properties: Connecting signals from Python to QML -

c# - DevExpress.Wpf.Grid.InfiniteGridSizeException was unhandled -

scala - 'wrong top statement declaration' when using slick in IntelliJ -